1. Field of the Invention
This invention relates to substrate structures, and, more particularly, to a substrate structure for carrying semiconductor components.
2. Description of Related Art
With the rapid development of the electronic industry, electronic products have gradually moved towards a multi-functional and high-performance trend. Such the technology currently used in the field of the chip package includes the flip chip package module (e.g., the chip scale package, referred to as CSP; the direct chip attached package, referred to as DCA, or the multi-chip module package, referred to as MCM) or the technology to stack the chips three-dimensionally to integrate into a three-dimensional integrated circuit (3D IC) chip by stacking.
FIG. 1 is a schematic cross-sectional view of a conventional semiconductor substrate 1. FIG. 1′ is a top schematic view of the semiconductor substrate 1.
As shown in FIGS. 1 and 1′, the conventional semiconductor substrate 1 is a wafer that comprises a substrate body 10, a wiring layer 11, and an insulating layer 12.
The substrate body 10 is defined with a plurality of layout areas 100, a sealing member 101 adjacent to the layout area 100, and a cutting area 102 adjacent to the sealing member 101. When a singulation process is carried out along the cutting area 102, the surface of substrate body 10 sometimes cracks. The cracks split along the surface of the substrate body 10 in the direction of the wiring area 100. The sealing member 101 prevents the crack from extending to the layout area 100.
The wiring layer 11 is formed on a portion of the layout area 100, and has a plurality of conductive pads 110.
The insulating layer 12 is formed on a portion of the layout area 100 and the wring layer 11, and the conductive pads 110 are exposed from the insulating layer 12. An under bump metallurgy (UBM) 14 may be formed on the conductive pads 110, and a conductive member (not shown), such as a soldering material or metal bumps, may be formed on the under bump metallurgy 14 in subsequent processes.
However, since the contact area of the substrate body 10 with the insulating layer 12 is large, and the substrate body 10 and the insulating layer 12 have different coefficients of thermal expansion (CTE). It is difficult for the semiconductor substrate 1 to uniformly release the thermal stress during the thermal cycle. Thus, the insulating layer 12 is easily delaminated from the substrate body 10 when the insulating layer 12 is stressed. As a result, the semiconductor substrate 1 is easily subject to warpage.
Although the sealing member 101 can provide a blocking effect during the singulation process, the cracks still make damages on the sealing member 101 and thus extend to the layout area 100, which leads to damage of the wiring layer 11.
Therefore, it is indeed an important issue as to how to override various deficiencies of related traditional technologies.